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CY7C1020V
32K x 16 Static RAM
Features
* 3.3V operation (3.0V - 3.6V) * High speed -- tAA = 10 ns * Low active power -- 540 mW (max., 12 ns) * Very Low standby power -- 330 W (max., "L" version) * Automatic power-down when deselected * Independent Control of Upper and Lower bytes * Available in 44-pin TSOP II and 400-mil SOJ (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 through A14). If byte high enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A14). Reading from the device is accomplished by taking chip enable (CE) and output enable (OE) LOW while forcing the write enable (WE) HIGH. If byte low enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O1 to I/O8. If byte high enable (BHE) is LOW, then data from memory will appear on I/O 9 to I/O16. See the truth table at the back of this datasheet for a complete description of read and write modes. The input/output pins (I/O1 through I/O16) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1020V is available in standard 44-pin TSOP type II and 400-mil-wide SOJ packages.
Functional Description
The CY7C1020V is a high-performance CMOS static RAM organized as 32,768 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Writing to the device is accomplished by taking chip enable (CE) and write enable (WE) inputs LOW. If byte low enable
Logic Block Diagram
DATA IN DRIVERS
Pin Configuration
SOJ / TSOP II Top View NC A 14 A 13 A 12 A 11 CE I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A 10 A9 A8 A7 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A6 A5 A4 A3 A2 A1 A0
32K x 16 RAM Array
I/O1 - I/O8 I/O9 - I/O16
COLUMN DECODER BHE WE CE OE BLE 1020V-1
A0 A1 A2 OE BHE BLE I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A3 A4 A5 A6 NC
ROW DECODER
A7 A8 A9 A10 A11 A12 A13 A14
SENSE AMPS
1020V-2
Selection Guide
7C1020V-10 Maximum Access Time (ns) Maximum Operating Current (mA) L Maximum CMOS Standby Current (mA) L 10 130 100 1 0.1 7C1020V-12 12 120 90 1 0.1 7C1020V-15 15 110 80 1 0.1 7C1020V-20 20 100 70 1 0.1
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
* CA 95134 * 408-943-2600 October 1996 - Revised April 13, 1998
CY7C1020V
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ............................................. -55C to +125C Supply Voltage on VCC to Relative GND[1] .... -0.5V to +4.6V DC Voltage Applied to Outputs in High Z State[1] .....................................-0.5V to VCC +0.5V DC Input Voltage ..................................-0.5V to VCC +0.5V
[1]
Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current..................................................... >200 mA
Operating Range
Range Commercial Industrial Ambient Temperature[2] 0C to +70C -40C to +85C VCC 3.0V - 3.6V 3.0V - 3.6V
Electrical Characteristics Over the Operating Range
7C1020V-10 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] Input Load Current Output Leakage Current VCC Operating Supply Current GND < VI < VCC GND < VI < VCC, Output Disabled VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC - 0.3V, VIN > VCC - 0.3V, or VIN < 0.3V, f=0 L Test Conditions VCC = Min., IOH = - 4.0 mA VCC = Min., IOL = 8.0 mA 2.0 -0.5 -1 -2 Min. 2.4 0.4 VCC + 0.3V 0.8 +1 +2 130 100 15 L 7 1 L 100 2.0 -0.5 -1 -2 Max. 7C1020V-12 Min. 2.4 0.4 VCC + 0.3V 0.8 +1 +2 120 90 15 7 1 100 Max. Unit V V V V A A mA mA mA mA mA A
ISB1
Automatic CE Power-Down Current -- TTL Inputs Automatic CE Power-Down Current -- CMOS Inputs
ISB2
Notes: 1. VIL (min.) = -2.0V for pulse durations of less than 20 ns. 2. TA is the "instant on" case temperature.
2
CY7C1020V
Electrical Characteristics Over the Operating Range (continued)
7C1020V-15 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] Input Load Current Output Leakage Current VCC Operating Supply Current GND < VI < VCC GND < VI < VCC, Output Disabled VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC - 0.3V, VIN > VCC - 0.3V, or VIN < 0.3V, f=0 L Test Conditions VCC = Min., IOH = - 4.0 mA VCC = Min., IOL = 8.0 mA 2.0 -0.5 -1 -2 Min. 2.4 0.4 VCC + 0.3V 0.8 +1 +2 110 80 15 L 7 1 L 100 2.0 -0.5 -1 -2 Max. 7C1020V-20 Min. 2.4 0.4 VCC + 0.3V 0.8 +1 +2 100 70 15 7 1 100 Max. Unit V V V V A A mA mA mA mA mA A
ISB1
Automatic CE Power-Down Current -- TTL Inputs Automatic CE Power-Down Current -- CMOS Inputs
ISB2
Capacitance[3]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max. 8 8 Unit pF pF
Notes: 3. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
3.3V OUTPUT 30 pF INCLUDING JIG AND SCOPE (a) OUTPUT Equivalent to: THEVENIN EQUIVALENT R2 255 R 481 R 481 3.3V OUTPUT 5 pF INCLUDING JIG AND SCOPE (b) 167 30 pF R2 255 GND <3ns
1020V-3 1020V-4
ALL INPUT PULSES 3.0V 90% 10% 90% 10% <3ns
1.73V
3
CY7C1020V
Switching Characteristics[4] Over the Operating Range
7C1020V-10 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z[5, 6] CE LOW to Low Z
[6] [5, 6]
7C1020V-12 Min. 12 Max.
7C1020V-15 Min. 15 Max. Unit ns 15 3 15 7 0 7 3 7 0 15 7 0 7 15 10 10 0 0 10 10 0 3 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7 9 ns ns
Description
Min. 10
Max.
10 3 10 5 0 5 3 5 0 12 5 0 5 10 8 7 0 0 7 5 0 3 5 7 8 12 9 8 0 0 8 6 0 3 0 0 3 0 3
12 12 6 6 6 12 6 6
CE HIGH to High Z
CE LOW to Power-Up CE HIGH to Power-Down Byte enable to Data Valid Byte enable to Low Z Byte disable to High Z Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z WE LOW to High Z
[6] [5, 6]
WRITE CYCLE[7]
6
Byte enable to end of write
Notes: 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 5. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write, and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
4
CY7C1020V
Switching Characteristics[4] Over the Operating Range (continued)
7C1020V-20 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z CE LOW to Low Z
[6]
Description
Min. 20
Max.
Unit ns
20 3 20 9 0 3 9 0 20 9 0 9 20 12 12 0 0 12 10 0 3 9 12
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
CE HIGH to High Z[5, 6] CE LOW to Power-Up CE HIGH to Power-Down Byte enable to Data Valid Byte enable to Low Z Byte disable to High Z Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z[6] WE LOW to High Z[5, 6] Byte enable to end of write
WRITE CYCLE[7]
Switching Waveforms
Read Cycle No.1
[8, 9]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
1020V-5
Notes: 8. Device is continuously selected. OE, CE, BHE, and/or BHE = VIL 9. WE is HIGH for read cycle.
5
CY7C1020V
Switching Waveforms (continued)
Read Cycle No.2 (OE Controlled)
ADDRESS tRC CE tACE OE BHE, BLE tDOE tLZOE tDBE tLZBE HIGH IMPEDANCE tLZCE V CC SUPPLY CURRENT tPU 50% tHZCE tHZBE DATA VALID tPD 50% IISB SB
1020V-6
[9, 10]
tHZOE
HIGH IMPEDANCE
DATA OUT
IICC CC
Write Cycle No. 1 (CE Controlled)
[11, 12]
tWC ADDRESS
CE
tSA
tSCE
tAW tPWE WE tBW BHE, BLE tSD DATAI/O tHD
tHA
1020V-7
Notes: 10. Address valid prior to or coincident with CE transition LOW. 11. Data I/O is high impedance if OE or BHE and/or BLE= VIH. 12. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
6
CY7C1020V
Switching Waveforms (continued)
Write Cycle No. 2 (BLE or BHE Controlled)
tWC ADDRESS
BHE, BLE
tSA
tBW
tAW tPWE WE tSCE CE tSD DATAI/O tHD
tHA
1020V-8
Write Cycle No. 3 (WE Controlled, OE LOW)
tWC ADDRESS
CE
tSCE
tAW tSA tPWE
tHA
WE tBW BHE, BLE tHZWE DATA I/O tLZWE tSD tHD
1020V-10
7
CY7C1020V
Truth Table
CE H L OE X L WE X H BLE X L L H L X L L L H L L H X H X X H BHE X L H L L H L X H I/O1 - I/O8 High Z Data Out Data Out High Z Data In Data In High Z High Z High Z I/O9 - I/O16 High Z Data Out High Z Data Out Data In High Z Data In High Z High Z Power-Down Read - All bits Read - Lower bits only Read - Upper bits only Write - All bits Write - Lower bits only Write - Upper bits only Selected, Outputs Disabled Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 10 Ordering Code CY7C1020V33-10VC CY7C1020V33L-10VC CY7C1020V33-10ZC CY7C1020V33L-10ZC 12 CY7C1020V33-12VC CY7C1020V33L-12VC CY7C1020V33-12ZC CY7C1020V33L-12ZC 15 CY7C1020V33-15VC CY7C1020V33L-15VC CY7C1020V33-15ZC CY7C1020V33L-15ZC CY7C1020V33-15ZI 20 CY7C1020V33L-20ZC Package Name V34 V34 Z44 Z44 V34 V34 Z44 Z44 V34 V34 Z44 Z44 Z44 Z44 Package Type Operating Range
44-Lead (400-Mil) Molded SOJ Commercial 44-Lead (400-Mil) Molded SOJ Commercial 44-Lead TSOP Type II 44-Lead TSOP Type II Commercial Commercial
44-Lead (400-Mil) Molded SOJ Commercial 44-Lead (400-Mil) Molded SOJ Commercial 44-Lead TSOP Type II 44-Lead TSOP Type II Commercial Commercial
44-Lead (400-Mil) Molded SOJ Commercial 44-Lead (400-Mil) Molded SOJ Commercial 44-Lead TSOP Type II 44-Lead TSOP Type II 44-Lead TSOP Type II 44-Lead TSOP Type II Commercial Commercial Industrial Commercial
Document #: 38-00543-B
8
CY7C1020V
Package Diagrams
44-Lead (400-Mil) Molded SOJ V34
44-Pin TSOP II Z44
(c) Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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